1. Field of the Invention
This invention relates to a buffer circuit. In particular, it relates to an output buffer circuit for a semiconductor integrated circuit.
2. Description of the Related Art
A conventional output circuit of a semiconductor integrated circuit device is constructed for example as shown in FIG. 1. In FIG. 1, reference numerals 11 to 14 represent CMOS inverters, constructed of P-channel MOS transistors Q1, Q3, Q5 and Q7 and N-channel MOS transistors Q2, Q4, Q6 and Q8. A signal D1 from the internal circuitry (not shown) is fed to the gate of P-channel load MOS transistor Q9 through inverters 11 and 12 and to the gate of N-channel drive MOS transistor Q10 through inverters 13 and 14. These MOS transistors Q9 and Q10 are series-connected between power source Vcc and ground Vss. Output signal Dout is obtained from the point of connection of these transistors Q9 and Q10. Inverters 11 and 13 are arranged to prevent both MOS transistors Q9 and Q10 from being ON at the same time which would allow a DC through-current to pass from power source Vcc to ground Vss. The change of output from high ("H") level to low ("L") level for inverter 11 takes place slightly before that of inverter 13, while the change of output from low ("L") level to high ("H") level for inverter 11 takes place slightly after that of inverter 13. This can be achieved for example by setting the dimension of MOS transistor Q1 to be smaller than that of MOS transistor Q2, and by setting the dimension (gate length and/or width) of MOS transistor Q5 to be larger than that of MOS transistor Q6. This makes the threshold value of inverter 11 lower than that of inverters 12 and 14, and the threshold value of inverter 13 higher than that of inverters 12 and 14.
The operation of the above circuit will now be described with reference to FIGS. 2(a) and (b). FIG. 2(a) shows the waveforms of the various signals when signal D1 from the internal circuitry changes from "L" to "H" level, and FIG. 2(b) shows the waveforms of the various signals when signal D1 changes from "H" to "L" level.
As shown in FIG. 2(a), at time-point t1, signal D1 from the internal circuitry rises from "L" level to "H" level. Thereupon, at time t2, output D2 of inverter 11 starts to change from "H" level to "L" level, and at time t3 output D4 of inverter 13 also starts to change from "H" level to "L" level. At the time-point t3 when output D2 of inverter 11 becomes lower than the circuit threshold value of inverter 12, output D3 of inverter 12 rises from "L" level to "H" level. This turns load MOS transistor Q9 OFF. On the other hand, at the time-point t4 when output D4 of inverter 13 becomes lower than the circuit threshold value of inverter 14, output D5 of inverter 14 rises from "L" level to "H" level. Consequently, drive MOS transistor Q10 turns ON, and output signal Dout falls from "H" level to "L" level at time-point t4. As shown in the Figure, a large peak current flows between the time points t4 and t5, which output signal Dout is being inverted.
In contrast, as shown in FIG. 2(b), signal D1 from the internal circuitry begins to fall at time t1 from "H" level to "L" level. At time t2, output D4 of inverter 13 starts to change from "L" level to "H" level, and at time t3 output D2 of inverter 11 also starts to change from "L" level to "H" level. At the time-point t3, when output D4 of inverter 13 has become higher than the circuit threshold value of inverter 14, output D5 of inverter 14 begins to fall from "H" level to "L" level. This turns drive MOS transistor Q10 OFF. Also, at the time-point t4 when output D2 of inverter 11 has become higher than the circuit threshold value of inverter 12, output D3 of inverter 12 begins fall from "H" level to "L" level. Consequently, load MOS transistor Q9 turns ON, and output signal Dout rises from "L" level to "H" level beginning at time-point t4. As shown in the Figure, a large peak current flows between the time-points t4 and t5 during which time output signal Dout is inverted. In general, however, in order to satisfy the specification for I.sub.OH (high level output current)/I.sub.OL (low level output current), the final-stage transistor in an output buffer circuit normally must be designed so as to permit a large current to flow. Specifically, in the FIG. 1 circuit described above, drive MOS transistor Q10 is designed so as to permit a large current flow in order to satisfy the I.sub.OL specification. Consequently, when drive MOS transistor Q10 changes from the OFF state to the ON state, a large current flows, i.e. there is an abrupt increase in current consumption. This generates self-noise, which is a cause of spurious circuit operation. Likewise, load MOS transistor Q9 is designed so as to permit alarge current to flow in order to satisfy the I.sub.OH specification. Consequently, when load MOS transistor Q9 changes from the OFF state to the ON state, a large current flows, i.e. there is an abrupt increase in current consumption. This also generates self-noise, which is a cause of spurious circuit operation.
As explained above, the output buffer circuit of FIG. 1 has a drawback, since it is designed for a large current flow in order to satisfy the specification for I.sub.OH (high level output current)I.sub.OL (low level output current). This results in an abrupt increase of current consumption on inversion of the output, generating self-noise which is a cause of spurious circuit operation.